1. Field of Invention
The present invention relates to a thin film transistor and a fabricating method thereof which is applied to a buried bus coplanar (BC) type wherein source and drain wires are located on a substrate.
2. Discussion of Related Art
FIGS. 1A to 1D show cross-sectional views of fabricating a thin film transistor according to a related art. Referring to FIG. 1A, first and second conductive layers are deposited successively on a substrate 100. A source electrode 10S and a drain electrode 10D, which are double layers, are formed by etching the first and second conductive layer by photolithography. Then, an insulating interlayer 12 which covers an exposed surface of the substrate is formed with an insulating substance.
Having been deposited on the insulating interlayer 12, an amorphous silicon layer is crystallized by laser crystallization. Then, an active layer 13 is formed by etching the crystallized silicon layer by photolithography.
Referring to FIG. 1B, a gate insulating layer and a third conductive layer are deposited successively on an exposed surface of the substrate. A gate electrode 15 is formed by etching the third conductive layer. In this case, the gate insulating layer 14 is also patterned to have the same pattern as the gate electrode 15. Thereafter, a source region 13S and a drain region 13D are formed by doping the active layer 13 with a first type of impurity which is of n type or a second type of impurity which is of p type.
Referring to FIG. 1C, a passivation layer covering an exposed surface of the substrate 100 is formed. Contact holes exposing the source and drain electrodes 10S and 10D and the source and drain regions 13S and 13D, respectively, are formed in the passivation layer 16 and the insulating interlayer 12.
Referring to FIG. 1D, after a transparent conductive layer has been deposited on an exposed surface of the substrate, a first interconnection wire 17-1 connecting the source electrode 10S to the source region 13S and a second interconnection wire 17-2 connecting the drain electrode 10D to the drain region 13D are formed by etching the conductive layer by photolithography. In the related art, the contact holes exposing the source and drain electrodes and the source and drain regions are formed by once etching the insulating interlayer and the passivation layer.
However, the double-layered insulating layer comprised of the passivation layer 16 and the insulating interlayer 12 has to be etched to expose the source and drain electrodes, while the passivation layer is only etched to expose the source and drain regions; that is, the passivation layer 16 is exposed to an etchant, such as an etching solution and an etching gas. Then, the passivation layer 16 starts to be etched away while the insulating interlayer 12 and the source and drain regions 13S and 13D, which are parts of the active layer, are exposed to the etchant. Thus, the etching process of forming the contact holes is terminated by exposing the source and drain electrodes 10S and 10D, as the insulating interlayer 12 is etched.
According to the related art, the thickness of an insulating substance layer near the contact holes, which are formed on the active layer, is different from that of the insulating substance layer near the other contact holes which are formed on the source and drain electrodes. Thus, the processing problems occur since the contact holes are formed by etching the insulating layer, which thickness is not uniform. These problems are explained in the following descriptions by referring to FIGS. 2-4.
FIG. 2 is a cross-sectional view explaining the problems caused during the step of forming contact holes wherein an insulating interlayer and a passivation layer are formed with the same substance. Referring to FIG. 2, an insulating interlayer and a passivation layer are formed with the same substance. When contact holes are formed by etching the layers, source and drain regions 13S and 13D in an active layer are damaged by an etchant or an etching gas for etching the insulating layers.
This is why the portions of the active layer are exposed to the etchant for a relatively long time despite the etchant having an excellent etch selectivity. In this case, the device characteristics are inferior due to the increased contact resistance between a transparent conductive layer and the damaged source and drain regions 13S and 13D.
In order to improve the device characteristics and to increase the device reliance by preventing H.sub.2 O penetration, the insulating interlayer and the passivation layer use a silicon oxide layer and a silicon nitride layer, respectively. Unfortunately, two kinds of problems show up due to different etching rates of the two layers against one etchant.
The first problem is caused by using an etchant which etches the passivation layer faster than the insulating interlayer.
FIG. 3 shows a cross-sectional view explaining the problem arising when contact holes are formed by using an etchant having a high etch rate in etching a passivation layer.
Referring to FIG. 3, a passivation layer 16 is etched selectively and primarily by an etchant having an etch selectivity, such as an etching solution or an etching gas, wherein priority prevails in the passivation layer 16 rather than an insulating interlayer 12.
The insulating interlayer 12 is exposed at a portion where the passivation layer 16 is removed, and then the insulating interlayer 12 is etched selectively. Yet, exposed to the etchant during the etching process of the insulating interlayer 12, the passivation layer 16 is still being etched. In this case, as the etchant etches the passivation layer faster than the insulating interlayer, the passivation layer is etched more than the insulating interlayer. As a result, regions of the contact holes become wider than those regions defined by a photoresist pattern, even though the process of etching the insulating interlayer 12 is carried out according to the design rule.
Moreover, as portions of the active layer are exposed to the etchant for a relatively long time, the source and drain regions 13S and 13D are damaged. In this case, device characteristics fail to show normality due to the increased contact resistance between the transparent conductive layer and the damaged source and drain regions 13S and 13D.
The second problem is caused by using an etchant which etches the insulating interlayer faster than the passivation layer.
FIG. 4 shows a cross-sectional view explaining the problem which arises when contact holes are formed by using an etchant having a high etch rate in etching an insulating interlayer.
Referring to FIG. 4, a passivation layer 16 is etched selectively and primarily by an etchant having an etch selectivity, such as an etching solution or an etching gas, wherein priority prevails in the insulating interlayer 12 rather than the passivation layer 16.
The insulating interlayer 12 is exposed at a portion where the passivation layer 16 is removed, and then the insulating interlayer 12 is etched selectively by the penetrating etchant. While the passivation layer 16 is still being etched as defined by a photoresist pattern PR, the insulating interlayer 12 is also etched by the penetrating etchant. In this case, as the etchant etches the insulating interlayer faster than the passivation layer, the insulating interlayer is etched more than the passivation layer. As a result, the passivation layer 16 is just etched as is defined by the photoresist pattern PR. Yet, the insulating interlayer may be over-etched.
For instance, the passivation layer and the insulating interlayer are made of silicon nitride, and the etching process is carried out by HF which etches silicon nitride faster than silicon oxide, whereby failure of interconnection wires of transparent conductive substance may arise due to the generation of undercutting.